1. Field of the Invention
The present invention relates to a semiconductor chip, and more particularly, to a semiconductor chip having a power supply line with a minimized voltage drop using an ESD dummy pad.
2. Description of the Related Art
A power supply should be provided in order to normally operate circuits implemented in a semiconductor chip. A power voltage supplied from an external unit of the semiconductor chip is supplied to an internal unit of the semiconductor chip through a power supply pad integrated in the semiconductor chip. The circuit implemented in the semiconductor chip may operate between a ground voltage and a unit power source or between a plurality of power voltages having different voltage levels. In this case, the ground voltage may be included or not in a plurality of power voltages having different voltage levels.
The externally supplied power voltage is delivered to internal circuits of the semiconductor chip through a power supply pad and a metal line connected to the power supply pad. In order to uniformly deliver the power voltage to the entire area of the semiconductor chip, the metal line used to supply the power voltage is typically laid out along edges of the semiconductor chip. Though the metal line for delivering the power voltage has a metal component, it still has a small amount of resistance component, and a voltage drop generated in the resistance component should be considered. Therefore, in order to minimize the resistance component, the width of the metal line for delivering the power voltage is designed to be larger than those of other metal lines used in the circuit. Unfortunately, no matter how large the width of the metal line for delivering the power voltage becomes, the larger distance from the power supply pad it has, the lower voltage level is inevitable in comparison with the voltage level of the power supply pad. This is because a serial resistance component increases as the distance from the power supply line increases.
A semiconductor chip for driving a single display panel has a significant number of signals supplied to the corresponding display panel. In consideration of symmetry of the delivered signals, the signals are preferably output from a pad mounted on one side of the semiconductor chip for driving the display panel. For this reason, a plurality of pads are concentrated on one side of the semiconductor chip for driving the display panel, and the semiconductor chip for driving the display panel is designed in a rectangular shape rather than a square shape.
FIG. 1 is a layout of a semiconductor chip having a rectangular shape.
Referring to FIG. 1, although the power supply pad area INPUT arranged near an upper center edge of the semiconductor chip is illustrated as a single rectangular shape, the number of pads arranged in the pad area INPUT may correspond to the number of supplied power voltages. For example, if two power voltages VDD and VSS are supplied, the power supply pad area INPUT may have at least two power supply pads. In FIG. 1, two power voltages VDD and VSS are delivered to internal circuits through a power supply main metal line which forms a closed loop along edges of the semiconductor chip. In order to supply the power voltages to the circuits (i.e., Channel Block and Control Block) arranged in the center of the semiconductor chip, a power supply branch metal line extended from the power supply main metal line laid out along the edges is used. A plurality of rectangles arranged in the edges of the semiconductor chip shown in FIG. 1 are pads for inputting/outputting signals.
Referring to FIG. 1, it is recognized that two power voltages VDD and VSS are supplied to the circuits (i.e., Channel Block and Control Block) arranged in the center of the semiconductor chip through the power supply branch metal lines extended from two power supply main metal lines VDD and VSS forming a closed loop along the edges of the semiconductor chip.
It would be readily anticipated that the voltage level of the power supply main metal line at a certain point (e.g., the A-point) located in the lower center edge of the semiconductor chip quite far from the power supply pad area INPUT is lower than the voltage level at the power supply pad area INPUT. This is because a voltage drop may be generated due to the resistance component in the power supply metal lines when the current flows from the power supply pad INPUT to the A-point (as in the arrow direction).
Particularly, since the power supply branch metal line extended from the power supply main metal line has a relatively narrow width, its resistance is relatively large. The power voltage is supplied to the internal circuits of the semiconductor chip through the power supply branch metal line. The more distant from the power supply pad the internal circuit is located, the more voltage drop may be generated.
Recently, there is tendency to reduce the amplitude of the signal exchanged in the circuit in order to lower power consumption in a semiconductor integrated circuit. Such a design strategy also reduces a design margin of the amplitude of the signal. If the level of the power voltage supplied to a reference circuit having a single function is different from the level of the power voltage delivered to a neighboring circuit which exchanges signals with the reference circuit, there may be errors in determining logic values of the signals exchanged between the reference circuit and the neighboring circuit.